Is Open Source RISC-V Ready to Take on Intel, AMD, and ARM in the Data Center?

While software is eating the world, open source hardware might soon be eating the data center. Definitely not tomorrow or next month, and probably not even next year, but sooner than you think, there might be as much open source hardware as the old-fashioned proprietary kind running data centers.

Need proof? Take a look at RISC-V, an open processor architecture.

A week or so ago at FOSDEM, an annual EU-based open source conference, the fabless RISC-V semiconductor company, SiFive, announced it's taking pre-orders through a campaign on Crowd Supply for HiFive Unleashed, a single-board computer (SBC) that runs Linux on the RISC-V-based quad-core 1.5GHz U540 system-on-a-chip, which the company announced in October.

The campaign, which runs through March 15, has so far raised nearly $95,000, with orders due to be shipped on June 30.

It's true that an SBC being presold in a crowdfunding campaign with a hefty price tag of $999 and based on a not-proven-ready-for-primetime silicon design isn't likely to end up in any commercial equipment anytime soon. But it's an important step for RISC-V, an architecture based on RISC (Reduced Instruction Set Computing) principles.

This SBC shouldn't be viewed so much as a product for production, but as a proof-of-concept, a chance for hardware developers to easily take the RISC-V instruction set architecture for a test drive and see what it can do outside the embedded market, where it's already getting some traction. Many top-tier chipmakers are already invested in the architecture; the nonprofit RISC-V Foundation, founded in 2015, now has more than 75 corporate members, including names like Google, NVIDIA, Samsung, Rambus, Qualcomm, Western Digital, and IBM.

Related:Will Open Compute Fall Victim to the Cloud’s Success?

Industry interest in the technology is understandable for a couple of reasons. Being open source, companies can use the architecture to develop products tailored to specific workloads without having to work around designs that are set in stone. And because it's released under the "permissive" BSD license, any tailoring can remain a secret sauce, and the entire chip can be released as proprietary if desired.

There's also now an elephant in any room where a chip design discussion is taking place: the Spectre and Meltdown processor vulnerabilities that have dominated the news this year. With Meltdown affecting something close to 100 percent of all processors from Intel, which controls about 90 percent of the server market, it wouldn't be a surprise to see OEMs deciding the time is right to introduce some diversity into the server room gene pool.

Additionally, in the snail-paced world of hardware design, RISC-V has been quick to market.

A couple of years back, the architecture started showing up embedded into field-programmable gate array (FPGA) designs and about a year ago made the jump into some microprocessing designs. Last October's U54-MC Coreplex from SiFive, with 4x 1.5GHz "U54" cores as well as a management core, was the first multi-core RISC-V design, the first with cache coherence and the first Linux-ready application processor.

RISC-V started as a project by Krste Asanović and David Patterson at University of California, Berkeley, in 2010, with some early funding coming from DARPA. These days, Asanović serves as board chairman at the RISC-V Foundation and Patterson as vice chair.

Asanović is also co-founder and chief architect at SiFive, which in addition to being behind the crowdfunded SBC markets RISC-V chips and related technology.

Since the start of the year, SiFive has been on a bit of a hiring binge. On January 22, the company announced that Intel VP Sunil Shenoy was coming on board as VP of hardware engineering. A week later, on January 30, a VP and business unit manager for semiconductor and networking company Microsemi joined SiFive as VP of operations. In May, 2017, the company announced it had raised $8.5 million in a Series B funding round led by Spark Capital, bringing total funding to $13.5 million..

According to the RISC-V Foundation, from a technical standpoint, the architecture should be able to compete with Intel, AMD, and ARM. The foundation says they see no reason why a RISC-V implementation should be any slower than x86 or ARM, and that "the ISA design should enable implementations to be somewhat more efficient than either." As for power consumption, the foundation says that depending "on the quality of the implementation," power efficiency should be able to more than match ARM's low energy use.

"In one point of comparison, the RISC-V Rocket core is twice as energy efficient as the most similar ARM implementation, the Cortex-A5," the foundation said in a Q&A.